1. Field of the Invention
The present invention relates generally to a system and method for designing integrated circuits or migrating integrated circuit designs from one technology node to another for fabrication by a semiconductor manufacturing process and, more particularly, to a system and method for providing optical proximity correction for integrated circuit design layouts.
2. Description of the Prior Art
The semiconductor manufacturing industry is continually evolving semiconductor device designs and fabrication processes and developing new processes to produce smaller and smaller geometries of the designs being manufactured. Semiconductor devices constituted by smaller geometries typically consume less power, generate less heat, and operate at higher speeds than those having larger geometries. Moreover, smaller geometries allow silicon chips to contain more circuit elements, and, hence, the integrated circuit (IC) can be more complex, and more copies of the same die can be produced on a single silicon wafer. Currently, a single IC chip may contain over one billion geometries. Consequently, IC designs and semiconductor fabrication processes are extremely complex, since hundreds of processing steps may be involved. Occurrence of a mistake or small error at any of the design or process steps may necessitate redesign or cause lower yield in the final semiconductor product, where yield may be defined as the number of functional devices produced by the process as compared to the theoretical number of devices that could be produced assuming no bad devices.
Improving time-to-market and yield is a critical problem in the semiconductor manufacturing industry and has a direct economic impact on the semiconductor industry. In particular, a reduced time-to-market and higher yield translate into earlier availability and more devices that may be sold by the manufacturer.
IC design layouts consist of a number of geometries in the form of polygons. Polygons are used to construct different features that are composed of portions of or whole polygons that are typically characterized by certain geometric properties such as dimensions. Each feature constitutes one or more shapes that represent one or more edges of a feature. A combination of features adjacent to each other forms a topological configuration that is often referred to as a pattern, or structure. Therefore, the IC layout can also be viewed as constituting a number of repeated patterns, and any number of such patterns constitutes a portion of the IC layout. These patterns of IC layouts are transferred to the silicon wafer predominantly through a process called lithography. In the most commonly used lithographic process referred to as photolithography, a mask or reticle having transparent and opaque regions representing structures in one IC layer is illuminated by a light source. The light emanating from the mask is then focused on a photoresist layer applied to the wafer. Then the wafer is developed to have portions of the resist removed and portions of the wafer etched, forming the geometrical patterns as desired. Typically, for IC designs with large feature dimensions, the patterns on the design are accurately transferred to the mask, and then accurately transferred to the wafer through the lithography process, culminating in a phenomenon commonly referred to as WYSIWYG (“What you see is what you get”).
With ever decreasing feature sizes, increasing pattern densities, and difficulty experienced in the advancement of IC manufacturing equipment, manufacturing of modern IC designs has encountered substantial impediments and concomitant yield problems within the near- and sub-wavelength regime, where the feature dimension is at or below the wavelength of the light source. Diffraction-limited imaging in the near- and sub-wavelength regime has caused the classical WYSIWYG paradigm to disappear. With the emergence of near- and sub-wavelength lithography, patterns projected to the wafer through the lithography process are severely distorted. Typical distortions include line edge displacement, which is common for line edge shapes, corner rounding, which is exhibited by corner shapes, and line end shortening, which is experienced with line end shapes, as illustrated in FIG. 1(a).
In view of the widening gap between design and manufacturability in the near- and sub-wavelength regime, the use of optical resolution enhancement techniques (RET) such as optical proximity correction (OPC) is prevalent in many of the design and manufacturing schema to produce feature sizes of 0.18 μm and smaller. Typically, a design tape-out, in the form of, for example, GDSII, is input to the RET implementation, e.g., an OPC data conversion, which generates new GDSII data using the input GDSII design tape-out as a reference.
OPC is a process in which the physical layout from design tape-out is modified to compensate for the pattern distortion caused by optical diffraction, resist development, etch, and other undesirable effects that occur during the lithography process. There are two known approaches to OPC. One is rule-based OPC, in which case correction rules are determined ahead of time, which specify how different geometrical shapes should be modified according to some simple measures associated with the shapes being considered, for example, feature width and spacing. There are predominantly three types of rule-based OPC. One type is hammerhead, that will be applied to line end shapes, as shown in FIG. 1(d), which corrects for line end shortening. Another type is serif, that will be applied to corners, as shown in FIG. 1(e), which corrects for corner rounding. The last type is edge bias, which corrects for line edge displacement, as shown in FIG. 1(f). The bias correction is a more generic form of correction, as more complex corrections can be represented by a collection of individual edge biases. For example, the serif or hammerhead corrections can be viewed as applying individual biases to two or three consecutive edge segments, with corners filled, as illustrated in FIG. 1(g) for the case of a serif. One polygon can contain a multitude of shapes that demand all three types of correction, as demonstrated in the example shown in FIG. 1(b). Rule-based OPC is usually geometry-based, and is simple and fast. However, rule-based OPC is not very accurate, and, hence, is used only for 0.25 μm or larger technology nodes or on non-critical layers of more advanced technology nodes (0.18 μm or smaller), such as metal, or layers that contain only relatively large geometries whose accuracy requirements are more relaxed. Moreover, generation of correction rules is non-systematic and often requires experience, and as the complexity of the geometries increases, the number of rules and possibly complexity of the rules increase as well, which makes them difficult to maintain.
The other OPC approach is model-based OPC. In model-based OPC, a lithography model, which captures the effects of optics and the general layout to the silicon pattern transfer process, is used to simulate the layout patterns and predict the corresponding patterns on the wafer, based on which the required correction to each geometrical shape is calculated and applied. The lithography model consists of a) an optical model and b) other process effects including chemical, etching, and other factors. An optical model typically operates within a finite range called a proximity range. When the optical image is simulated for a location, commonly referred to as an evaluation point, only layout geometries within a radius of the proximity range centered around the evaluation point are considered, and those geometries outside of the range are ignored. A calibrated lithography model incorporates the optical model and the other process effects. To obtain a calibrated model, test masks are illuminated, wafer images are formed, and measurements are made, followed by data fitting. The lithography model is independent of physical layout.
The model-based OPC process typically involves a step referred to as dissection, where polygon edges are broken into edge segments which can be moved individually to correct each segment. Evaluation points are specified on the segments where the models are evaluated to calculate certain wafer characteristics, such as edge displacement, as illustrated in FIG. 1(c). The required edge movement is calculated on-the-fly so that the simulated edge displacements are minimized. Due to the use of a model and a correction algorithm, the correction does not require correction rules a priori, and is usually more accurate than one corrected by a rule-based approach. On the other hand, due to finer granularity of the correction, the resulting corrected layout by a model-based approach is typically more complex than that by a rule-based approach. Accordingly, full model-based OPC is generally used for critical layers of designs of 0.18 μm or smaller.
Because a critical layer may also contain non-critical features for which a rule-based approach would suffice, a hybrid OPC approach is sometimes used that achieves reduction in OPC turnaround time and also simplification of OPC complexity. In such selective hybrid OPC, as disclosed in U.S. Pat. No. 6,584,609, a portion of the layout, typically containing non-critical or large features, is corrected by rule-based OPC, and a different portion of the layout, typically containing critical or small features, is corrected by model-based OPC. The more areas that require rule-based OPC, the faster the turnaround time, and the less complex the output. However, determination of the selection rules, like the determination of the correction rules, is still very much a manual process, and is usually a time-consuming and ad hoc process. Moreover, the accuracy performance of these rules is difficult to quantify a priori. Hence, it is difficult to predict the accuracy of the correction results when they are applied.
Thus, it would be desirable to provide an IC design system and method for generating selection and correction rules for the rule-based OPC in hybrid OPC applications. In particular, a model-based approach that provides systematic pattern characterization and rule generation is needed that also allows quantitative prediction of the corresponding OPC results. It is to this end that the present invention is directed. The various embodiments of the present invention provide many advantages over conventional IC design methods and systems.